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release time:2024-04-09 Hits: Popular:AG11 battery
6LR61 batterylow voltage indication and control circuit design
Most portable electronic products are powered by rechargeable batteries, but generally there is no 6LR61 batterylow-voltage indication circuit, which often causes the 6LR61 batteryto over-discharge and damage the rechargeable battery, and also affects the normal operation of the circuit due to low 6LR61 batteryvoltage. Based on this situation, the author designed a 6LR61 batterylow voltage indication circuit and can control the shutdown of the voltage regulator. This circuit uses a voltage detector IC and a linear regulator IC with shutdown control.
Introduction to the two ICs 1. Voltage detector The voltage detector with CMOS output structure is a three-terminal integrated circuit that requires no external power supply or external components. The device has ultra-low power consumption and a quiescent current of 13A; the detection voltage VDET accuracy is 2% to 2.4%; the internal comparator has hysteresis characteristics to ensure working stability. The relationship between the hysteresis voltage VHYS and the detection voltage VDET is about VHYS≈0.05VDET.
The voltage detector of CMOS complementary output structure is shown in Figure 1. VDD is the input detection voltage terminal, VSS is the ground, and VOUT is the output terminal of the voltage detector. When VDD>VDET, VOUT≌VDD; when VDD drops below the detection voltage, VOUT≈0V. When VDD is boosted from less than VDET, when VDD=VDET+VHYS, VOUT=VDD. Its characteristics are shown in Figure 2. When VDD<0.91V, the internal circuit has an abnormal output due to the low operating voltage and is in a non-working area (as shown by the slash in Figure 2). The detection voltage range of the voltage detector is from 0.9V to 6.3V, and there is a variety with an interval of almost 0.1V. Voltage detectors are available in TO-92 packages, SOT-89 packages and SOT-23 packages. The SOT-89 package is shown in Figure 3.
2. Linear voltage regulator with shutdown control. The linear voltage regulator with shutdown control is shown in Figure 4. SHDN is the shutdown control terminal: when the level is increased, the power supply works normally; when the level is increased low, the power supply is turned off. In the off state, power consumption is low, generally less than 1uA.
6LR61 batterylow voltage indication and control circuit The 6LR61 batterylow voltage indication and control circuit is shown in Figure 5. The circuit is powered by 4-cell NiCd or NiMH batteries. The linear voltage regulator with shutdown control outputs 3.6V, and the voltage difference is 360mV when outputting 100mA. The power is turned off when the SHDN terminal is driven to a low level. The detection voltage of the CMOS output voltage detector is VDET=4V, and the accuracy is 2.4%.
The rated voltage of the 4-cell 6LR61 batteryis 4.8V, and the terminal discharge voltage is 4V. When the 6LR61 batteryvoltage is greater than 4V, the voltage detector output terminal (pin 1) outputs high level (≈VDD). This high level is added to the SHDN terminal to make the power supply work normally; because the VOUT terminal voltage is close to the VDD voltage, the LED does not light up. When the 6LR61 batteryvoltage drops to 4V, the advantage of the voltage detector's VDD circuit is that charging utilizes the battery's discharge energy to prevent the 6LR61 batteryfrom over-discharging and preventing the load circuit from working abnormally or having excessive errors due to the 6LR61 batterybeing too low; Compared with the general circuit, only one voltage detector, one resistor and one LED are added, which occupies a small area of the printed circuit board and the cost is not high.
Design Calculation If the output voltage of the voltage regulator is VOUT and its maximum voltage difference is VDD, then its minimum input voltage VINmin=VOUT+VDP. In order to ensure the normal operation of the power supply, the VDET of the voltage detector should satisfy VDET=VINmin. The battery's termination discharge voltage VBATmin should satisfy VBATmin≥VDET.
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