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　　The principles and implementation methods of three TDC circuits

　　This article introduces different types of time measurement methods and discusses the circuits and implementation techniques used to achieve high-precision time measurement. Through these methods, time measurement at the picosecond (ps) level can be achieved to meet the needs of different applications. As a basic physical quantity, time plays an extremely important role in space exploration, high-energy physics, remote sensing and telemetry, and the measurement of flow and distance. The time measurement discussed in this article refers to the measurement of a time period, that is, the measurement of the time interval from the start signal start to the end signal stop. There are many ways to achieve high-precision time measurement through electronic circuits, and there are many names for such circuits, including time interval table (TIM), time digitizer (TImedigiTIzer), time counter (TC), time-to-digital converter (TDC) etc. The most commonly used name at present is TDC[1~2]. TDC circuits have different principles and implementation methods. Currently, common methods include the tapped delay line method, the vernier method, and the capacitor charging and discharging method.

　　Time measurement based on clock pulses

　　The simplest TDC circuit is to sample and count the time range to be measured through the clock signal, and calculate the time value based on the count value. This method is the direct counting method, and the minimum resolution of time measurement is the clock cycle used for counting. In order to improve the measurement resolution, the frequency of the clock can only be increased. However, since the generation and stable transmission of ultra-high-frequency clock signals are difficult, it is difficult to achieve ps-level precision measurement through this method. This weakness makes it impossible to achieve the desired performance when needed. Used for precision time measurement. However, this method can often be used in combination with other measurement methods introduced later to learn from each other's strengths and weaknesses.

　　Time measurement based on the tapped delay line method

　　The principle of the tapped delay line method is to transmit the measured start signal through the delay line, and detect the position it passes to within the measured time period through the tapped signal, thereby judging the time measurement result. The signal delay time between adjacent taps is the minimum resolution of the measurement. When implemented in a circuit, a delay line is generally constructed by delay cells, and the measured resolution is the delay time of these cells. In integrated circuits, the commonly used circuit unit is an inverter. Under currently commonly used integrated circuit process conditions, this delay time can be of the order of about 101~102ps. For most measurements, this resolution is sufficient. requested.

　　A basic tapped delay line time measurement circuit is shown in Figure 1. Among them, a stop signal is used at the tap to sample the start signal transmitted through the delay line. According to the sampling results Q0~Qn (thermometer type code), the position where the start signal is transmitted through the measured time period can be known. From this, according to each The delay time τ of the unit is calculated from the time interval being measured. The range of the tapped delay line method is determined by the length of the delay line (the number of delay cells). This structure is the basis for many time measurement circuits and can be combined with other technologies to form different practical circuit forms.

　　Time measurement based on vernier method

　　Time measurement can also be done using methods similar to mechanical vernier calipers. It uses two delay lines, where the delay times of the units are τ1 and τ2 respectively. There is a small but fixed delay difference between τ1 and τ2. The start signal and the end signal are transmitted through these two delay lines respectively, and the start and end signals are detected. When the end signal coincides during the transmission process, the time difference between the start and the end can be obtained through the position of the coincidence point. The basic principle of the vernier method time measurement circuit is shown in Figure 2(a), in which trigger sampling is used to compare whether the start and end signals coincide. In other designs, a special signal coincidence detection circuit is used instead of a flip-flop. A signal coincidence detection circuit form is shown in Figure 2(b) [3]. According to the two output signals of this circuit, output 1 and output 2 The order in which signals arrive can be judged to achieve coincidence judgment.

　　In the basic vernier method time measurement circuit, when it is detected that the start and stop signals after transmission through the delay line overlap at a certain point, it can be known through calculation when TstopTstart<τ1:

　　Tstop-Tstart=(n-1)(τ1τ2)

　　where n is the number of comparisons passed. The resolution of this measurement method is the time difference of the delay units in the two delay lines, that is, (τ1τ2). When designing the circuit, it must be ensured that τ1>τ2. Its range is determined by the number of delay units and τ1 and τ2. It can be seen that this method can achieve higher measurement resolution than the tapped delay line method, provided that the units in the two delay lines used for measurement have stable delays. In order to achieve this goal, pLL or DLL are often used. Generate delay lines with stable delays [4-5].

　　Time measurement based on capacitor charge and discharge method

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