Nickel Hydride No. 5 batteries

　　Design of Nickel Hydride No. 5 batteries and lithium polymer battery protection circuit

　　During discharge, the chip monitors the V- terminal voltage at the same time. When the V- terminal voltage is higher than the discharge over-current detection voltage but lower than the short-circuit detection voltage due to excessive current, the chip enters the discharge over-current protection state; when the V- terminal voltage is higher than the short-circuit detection voltage, the chip enters short-circuit protection state. At this time, the DOUT terminal output changes from high potential to low potential, turning off MD to prevent strong current from flowing through the circuit. In Figure 1, R1 and C1 play the role of smoothing, filtering and suppressing the voltage fluctuation of an external charger or a secondary battery connected in parallel with it. The resistors R1 and R2 are current-limiting resistors when the battery is reversely charged or the charging voltage of the charger exceeds the absolute limit rated charging voltage of the chip. The system mainly includes overcharge detection circuit (VD1), over-discharge detection circuit (VD2), discharge over-current detection circuit (VD3) and short-circuit detection circuit, level conversion circuit, reference circuit, oscillation circuit and bias circuit. 3 Circuit Design Since the protection circuit relies on the battery to supply its power supply voltage, in order not to affect the battery's standby time, a battery protection circuit with low power supply voltage and low power consumption should be designed as much as possible.

　　3.1 Detection circuit design Since the detection circuits VD1, VD2, and VD3 have similar principles, the design of the over-discharge detection circuit (VD2) is used as an example for analysis. In order to meet the requirement of low power consumption of the entire chip, the circuit can be designed to operate in a sub-threshold state, effectively reducing its operating current and voltage.

　　The over-discharge detection circuit (VD2) can be implemented using a two-stage open-loop comparator, as shown in Figure 2. Differential inputs should be used in the design and the gain should be increased as much as possible to meet accuracy requirements. In this circuit, the first stage is a differential amplifier composed of MN1, MN2, Mp1, Mp2, MN3, and MN4. The second stage is a single-stage amplifier composed of MP5 and MN5. The preamplifier amplifies the input differential mode signal, and the subsequent stage further amplifies the output of the preamplifier to reach the output level of the digital signal. The DC gain of this comparator circuit is: At the same time, performance such as transmission delay, output voltage slew rate, input common mode range, etc. must also be considered. Since large bias current and small capacitance can improve the slew rate and shorten the delay time, high speed can be achieved by increasing the bias current. However, generally speaking, high-speed comparators also have higher power consumption. Therefore, a trade-off must be made between power consumption and speed when designing. Compared with the comparator in the saturation region, the delay time of the comparator operating in the sub-threshold region increases significantly. This is mainly due to the smaller bias current operating in the sub-threshold region and the longer time required to charge and discharge the capacitor. , thus making the delay time longer. This comparator has an ICMR (input common mode range) similar to that of a differential amplifier, and its minimum input voltage should be less than the over-discharge detection reference voltage. 3.2 Bias circuit design The bias circuit is used to provide a stable and high-precision reference voltage for the detection circuit to detect overcharge, overdischarge, discharge overcurrent and other states. In this paper, a low-power reference circuit is designed, as shown in Figure 3.

　　Since the depletion-mode NMOS tube has a negative threshold voltage and is still in operation when VGS=0, this feature can effectively reduce its operating voltage and power consumption. Therefore, the reference circuit uses series-connected depletion mode NMOS transistors MN1-MN4, series-connected enhancement mode NMOS transistors MN5-MN9, MN11-MN12 and resistors R1 and R2 to form a VGS-based reference voltage circuit. The output of the reference circuit is Detect the reference voltage signal VREF at the inverting end of the comparator. Since the depletion threshold voltage in this circuit is negative and the gate-source voltage is always 0, the depletion-mode tube always works in the saturation region. And its current value is constant: At the same time, in order to meet the low power consumption requirements of this circuit, the enhancement tube in the circuit should be made to work in the sub-threshold area as much as possible. As shown in Figure 3, based on the offset effect and the increase in source potential, the MN5 tube operates in the sub-threshold region. That is, for enhancement mode NMOS transistors, VTH decreases as the temperature increases, while for depletion mode NMOS transistors, VTH is a negative value, and its absolute value increases as the temperature increases. It can be deduced that when appropriate parameters are selected, the temperature drift of this circuit can be controlled within a smaller range. 3.3 Design of the rest 3.3.1 Delay circuit In order to prevent interference signals from causing misoperation of the protection circuit, the system sets corresponding delay times for different abnormal states. This delay time is realized by the oscillation circuit and the counter. The oscillation circuit adopts a three-stage ring oscillator structure, each stage of which is composed of an inverter and a capacitor. When the oscillation circuit is working normally, it outputs an oscillating square wave to the counter, and when it does not work, it outputs a high level. The counter is formed by cascading D flip-flops. 3.3.2 Level conversion circuit At the same time, in order to ensure that the charging control tube MC is effectively turned off in the overcharge state, a level conversion circuit is used to make the output COUT terminal the fourth-level inversion of the logic circuit output signal, thereby making the COUT terminal low-voltage. Flat from VSS to V-. 3.3.3 Some circuits in the standby state chip are equipped with enable terminals, which are logic circuit outputs. When the protection circuit enters the over-discharge protection state, the enable terminal changes from high potential to low potential, the corresponding circuit is closed, and the chip enters standby state, thereby greatly reducing current consumption and power consumption.

　　4 Simulation results and analysis This chip adopts 0.6μm standard CMOS process. Simulations were performed using the 49-level HSpICE model. Figure 4 is the overcharge protection and recovery waveform diagram, and Figure 5 is the overdischarge protection and recovery waveform diagram. During normal operation, the current consumption of the chip is 2.11μA, while the current consumption in standby mode is only 0.03μA. The voltage detection accuracy of overcharge and overdischarge is about 25mV.

　　5 Conclusion This article is based on the principle of a full-function battery protection circuit and sets up corresponding protection mechanisms for abnormal conditions such as over-discharge, over-charge, discharge over-current, and load short circuit. In order to meet the low power consumption requirements, a reference circuit and comparator based on the sub-threshold area are designed, and a standby state is set. After simulation verification, this chip meets the functional and performance design requirements and has been successfully taped out.

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