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18650 battery flat top circuit design tips: how to maximize power efficiency
In this power supply design tip, we will discuss how to maximize power supply efficiency for a specific load current using the same number of stages. We recommend using the following output current function to calculate power losses:
The next step is to take the simple expression above and put it into the efficiency equation:
In this way, the efficiency of the output current is optimized. This optimization can produce an interesting result.
Efficiency will be maximized when the output current is equal to the following expression.
The first thing to note is that term a1 has no effect on the current at maximum efficiency. This is because it is associated with losses that are proportional to the output current at, for example, the diode junction. Therefore, when the output current increases, the above losses and output power also increase, without affecting the efficiency. The second thing to note is that optimal efficiency occurs at a certain point where fixed losses and conduction losses are equal. This means that optimal efficiency can be achieved by simply controlling the components that set the a0 and a2 values. We still need to work hard to reduce the value of a1 and improve efficiency. The results of controlling this term are the same for all load currents, so like the other terms, optimal efficiency does not occur. The goal of item a1 is to minimize costs while controlling them.
Table 1 provides an overview of the various power loss terms and their associated loss factors, and provides some trade-offs for optimizing power supply efficiency. For example, the choice of a power MOSFET's on-resistance affects its gate drive requirements as well as Coss losses and potential snubber losses. Low on-resistance means that gate drive, Coss and snubber losses increase inversely. Therefore, you can control a0 and a2 by selecting MOSFETs.
The next bit of the algebraic expression substitutes the optimal current back into the efficiency equation, and the maximum efficiency is solved as:
The last two terms in this expression need to be minimized to optimize efficiency. Item a1 is simple, just minimize it. The last term enables partial optimization. If you assume that a MOSFET's Coss and gate drive power are related to its area, while its on-resistance is inversely proportional to area, you can choose the optimal area (and resistance) for it. Figure 12.1 shows the die area optimization results. When the die area is small, the MOSFET's on-resistance becomes the efficiency limiter. As the die area increases, so do the drive and Coss losses.
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